Image processing device

ABSTRACT

The image processing apparatus according to the present invention comprises: DMA control means  112  having image input/output processing means  100 , an external memory  111 , DMA setting holding means  113 , address generating means  114 , DRAM control means  115 , DMA request generating means  119 , and DMA request adjusting means  120 ; a processor  116  including encoding/decoding processing means  117 ; and a DMA bus  118  as shown in FIG.  1.    
     In the image processing apparatus so constructed, a transfer data group which can be previously subjected to DMA scheduling is divided into burst transfer units, and the DMA request generating means periodically issues the DMA request in the burst transfer units and performs DMA of the transfer data which cannot be subjected to the DMA scheduling during the period that the DMA of the transfer data is not performed, thereby avoiding concentration of specific DMA.

TECHNICAL FIELD

The present invention relates to an image processing apparatus having adata transfer control apparatus, which can improve the data transferefficiency of a memory which shares different types of data by a timedivision method.

BACKGROUND ART

In recent years, systems utilizing image communication such as a visualtelephone and a television conference system has been becoming of greatinterest. Typically, a communication line utilized in this system has alow transmission speed. Therefore, an image encoding/decoding techniqueis essential for the transmission of image data of massive data amount,and actually, various kinds of encoding/decoding methods have beendevised.

Further, in these circumstances, it has been desired to provide an imageprocessing apparatus which performs image encoding/decoding processingby a processor which can be controlled by programs, and which canflexibly correspond to various encoding/decoding methods by replacementof a control program.

Further, in video compression and decompression processings in theconventional image processing apparatus, complicated data transfer, suchas obtaining image data of a part of a region, has been required. Suchcomplicated data transfer is realized on the basis of a large amount ofcontrol information. Therefore, there is a problem that, after thecontrol information is obtained after the data transfer which ispresently being executed is completed, the next data transfer isexecuted, the larger the number of control information is, the longerthe time interval between the completion of the data transfer and thestart of the next data transfer is, thereby resulting in a deteriorateddata transfer efficiency.

In order to solve this problem, in the conventional image processingapparatus, there is provided a data transfer control apparatus in whichthere are provided data transfer control information obtaining means andreservation data transfer information holding means, the controlinformation required for the next data transfer is acquired while thedata transfer is being executed to be stored in the reservation datatransfer information holding means, and when the data transfer now beingexecuted is completed, the next data transfer can be immediately startedon the basis of the control data prepared in the reservation datatransfer information holding means.

An example of an image processing apparatus X which is conventionallyused as described above and performs encoding/decoding processing by aprocessor which can be controlled by programs will be described withreference to FIG. 8.

FIG. 8 is a structural block diagram illustrating the image processingapparatus X. The image processing apparatus X includes imageinput/output processing means 500, input control means 501 forperforming resolution conversion of the input image and image noiseremoval processing using the input image and the previous frame image,an input image buffer 502 which temporarily holds the output image dataof the input control means 501 before transferring the data from theinput control means 501 to an external memory 511, a previous frameimage buffer 503 which temporarily holds the previous frame image datastored in the external memory 511 before giving the same to the inputcontrol means 501, a sub-picture generation input buffer 504 whichtemporarily holds the display image data stored in the external memory511 before giving the same to sub-picture generating means 505,sub-picture generating means 505 for performing resolution conversion ofthe display image data stored in the external memory 511 into thesub-picture, a sub-picture generation output buffer 506 whichtemporarily holds sub-picture image data which is generated by thesub-picture generating means 505, before transferring the data from thesub-picture generating means 505 to the external memory 511, asub-picture buffer 507 which temporarily holds the sub-picture imagedata stored in the external memory 511, before giving the same todisplay control means 510, a main picture buffer 508 which temporarilyholds the display image data which is stored in the external memory 511,before giving the same to the display control means 510, a graphicsbuffer 509 which temporarily holds graphics data stored in the externalmemory 511, before giving the same to the display control means 510, anexternal memory 511 which stores data, with performing regionsegmentation for different types of image data, such as encoding targetimage, a sub-picture, a display image, and graphics, DMA control means512 for controlling a data transfer between the image input/outputprocessing means 500 or the processor means 516 and the external memory511, i.e., a Direct Memory Access (hereinafter, referred to as “DMA”),DMA settings holding means 513 for holding respective settinginformation for performing the DMA control, address generating means 514for generating an address of the external memory 511 in accordance withthe DMA setting information, DRAM control means 515 for controllingwriting and reading of the external memory 511, the processor means 516which can be controlled by programs, encoding/decoding processing means517 for processing an image of the external memory 511 or code data byprogram control, and a DMA bus 518 which performs DMA between the inputimage buffer 502, the previous frame image buffer 503, the sub-picturegeneration input buffer 504, the sub-picture generation output buffer506, the sub-picture buffer 507, the main picture buffer 508, and thegraphics buffer 509, the processor means 516, and the external memory511.

Hereinafter, the operation of the image processing apparatus X soconstructed will be briefly described.

Initially, an input image is always input to the input control means 501with synchronized with a video synchronizing signal at a constant rate.

After the input image is input to the input control means 501, the inputcontrol means 501 performs resolution conversion of the input image intothe image size to be encoded. Thereafter, the input control means 501temporarily stores the same in the input image buffer 502.

In addition, the input control means 501 performs removal processing ofnoises in the input image by using the previous frame image. In thiscase, the previous frame image stored in the external memory 511 issubjected to the DMA to the previous image buffer 503, and noise removalprocessing is performed while reading the previous frame image from theprevious frame image buffer 503.

When the display image stored in the external memory 511 is displayed asthe sub-picture, the sub-picture generating means 505 performsresolution conversion of the display image transferred from the externalmemory 511 through the sub-picture generation input buffer 504 into thesub-picture size, and temporarily stores the same in the sub-picturegeneration output buffer 506. Thereafter, the stored display image istransferred from the sub-picture generation output buffer 506 to theexternal memory 511.

The display control means 510 reads the sub-picture, the main picture,and the graphics data from the sub-picture buffer 507, the main picturebuffer 508, and the graphics buffer 509, respectively, and, afterdisplay composition, synchronizes the same with the video synchronizingsignal as the display image to output at a constant rate.

The processor means 516 transfers image data of an encoding target,which is stored in the external memory 511, to the inside of theprocessor, performs encoding processing, and transfers the code data tothe external memory 511. Further, the processor means 516 transfers thecode data stored in the external memory 511 to the inside of theprocessor, performs decoding processing, and transfers the same to theexternal memory 511 as the display image data.

The DMA among the external memory 511, the input image buffer 502, theprevious frame image buffer 503, the sub-picture generation input buffer504, the sub-picture generation output buffer 506, the sub-picturebuffer 507, the main picture buffer 508, and the graphics buffer 509,and the processor means 516 is executed by the processor means 516making DMA request to the DMA control means 512.

When the DMA request is made by the processor means 516, the DMA controlmeans 512 gives the DMA settings information which is set in DMA settingholding means 513 to the address generation means 514.

The address generating means 514 generates an access address of theexternal memory 511 on the basis of the received DMA settinginformation, and gives the same to the DRAM control means 515.

The DRAM control means 515 controls reading or writing of either of theinput image buffer 502, the previous frame image buffer 503, thesub-picture generation input buffer 504, the sub-picture generationoutput buffer 506, the sub-picture buffer 507, the main picture buffer508, and the graphics buffer 509, or the processor means 516, andwriting or reading of the external memory 511.

The external memory 511, the input image buffer 502, the previous frameimage buffer 503, the sub-picture generation input buffer 504, thesub-picture generation output buffer 506, the sub-picture buffer 507,the main picture buffer 508, the graphics buffer 509, and the processorbuffer 516 are connected by a single DMA bus, and the DMA with theexternal memory 511 is performed by the time division method.

However, in a structure of the conventional image processing apparatus Xas described above, all the DMA scheduling with the external memory 511is performed by the processor means 516. Therefore, there has been aproblem that the publication timing of the DMA request sometimes becomesirregular in accordance with a processing load of the processor means516.

On the other hand, image input/output of image input/output processingmeans 500 must be synchronized with the video synchronizing signal andbe input and output at the constant rate. Therefore, in order to absorbthe irregularity of the DMA, the memory capacity of each buffer isincreased, and the measures such as the speed-up of the transfer speeddue to the extension of the DMA bus width and the raise of an operatingfrequency are taken. However, here, there has been a problem such as theincrease in the circuit scale and the complication of the circuitdesign.

Further, in a data transfer control apparatus used in the conventionalimage processing apparatus, after completing the data transfer which isbeing executed, the next data transfer is executed. Therefore, there hasbeen a problem, for example, that a transfer execution start of urgentlyrequired data is delayed, and therefore, data cannot be obtained withinthe required time.

The present invention is made to solve these problems, and has itsobject to provide an image processing apparatus which enables the datatransfer control in which the DMA is preformed while sharing a singlememory by comprising the data transfer control apparatus which can startdata transfer with high priority without waiting for the completion ofthe data transfer which is being executed, and more particularly, animage processing apparatus which enables the data transfer control whichrealizes the efficient DMA by preventing a specific DMA from beingconcentratively generated as well as suppressing the increase in thecircuit scale.

DISCLOSURE OF THE INVENTION

In an image processing apparatus of claim 1 of the present inventioncomprising: image input/output processing means for inputting/outputtingan image; a memory which shares different types of image data by timedivision; encoding/decoding processing means for encoding or decodingdata stored in the memory; and data transfer control means forcontrolling a data transfer from the memory to the image input/outputprocessing means or the encoding/decoding processing means, a transferdata group which can be subjected to direct memory access scheduling isdivided into burst transfer units, the direct memory access in the bursttransfer units is periodically performed, and the transfer data whichcannot be subjected to direct memory access scheduling is subjected tothe direct memory access during the period that the transfer data is notsubjected to the direct memory access.

According to an image processing apparatus of claim 2 of the presentinvention, in the image processing apparatus of claim 1, the bursttransfer unit is obtained by combining a block unit into which thetransfer data which can be previously subjected to the direct memoryaccess scheduling is equally divided, and the block unit is periodicallysubjected to the direct memory access.

In an image processing apparatus of claim 3 of the present inventioncomprising: image input/output processing means for inputting/outputtingan image; a memory which shares different types of image data by a timedivision method; and data transfer control means for controlling a datatransfer from the memory to the image input/output processing means orthe encoding/decoding processing means, the data transfer control meanscomprises: encoding/decoding processing means for encoding or decodingdata stored in the memory; direct memory access request generating meansfor generating a transfer timing of data which can be previouslysubjected to the direct memory access scheduling; direct memory accessrequest adjusting means for performing adjustment so as to interrupt thedirect memory access with the encoding/decoding processing means andpreferentially execute the direct memory access of the imageinput/output processing means in the case where the direct memory accessrequest is made from the direct memory access request generating means;direct memory access settings holding means for holding settinginformation of the direct memory access; data transfer executing meansfor generating an address of the memory on the basis of direct memoryaccess setting information to transfer data by an instruction from thedirect memory access request adjusting means; and memory control meansfor controlling writing or read-out of the memory.

According to an image processing apparatus of claim 4 of the presentinvention, in the image processing apparatus of claim 3, the directmemory access request generating means comprises: frame detecting meansfor detecting the head of the frame; first line detecting means fordetecting the head of the line inside the frame; clock counting meansfor receiving a line head signal from the first line detecting means toreset a discrete value, and thereafter counting an operation clock; linecounting means for receiving a frame head signal from the framedetecting means to reset a discrete value, and thereafter counting aline head signal from the first line detecting means; second linedetecting means for detecting a start time of the direct memory accessin burst transfer units which can be previously subjected to the directmemory access scheduling from the discrete value of the clock countingmeans; line cycle counting means for resetting the discrete value by theframe head signal from the frame detection means and a signal after onecycle end and counting the line detecting signal from the second linedetecting means; efficient vertical period detecting means for detectingan efficient line period from the discrete value of the line countingmeans and a detecting signal of the second line detecting signal;efficient line detecting means for detecting an efficient line from thediscrete value of the line cycle counting means; and request signaldetecting means for detecting a request timing of the direct memoryaccess from the discrete value of the clock counting means, andgenerates a direct memory access request signal from a signal output ofthe efficient vertical period detecting means, a signal output of theefficient line detecting means, and a signal output of the requestsignal detecting means.

As described above, according to the image processing apparatus ofclaims 1 through 4 of the present invention, DMA control meanscomprises: DMA request generating means for generating a transfer timingof data which can be previously subjected to DMA scheduling; and DMArequest adjusting means for performing adjustment so as to interrupt theDMA of the processor means and preferentially execute the DMA with theimage input/output processing means in the case where the DMA request ismade from the DMA request generating means. A transfer data group whichcan be previously subjected to DMA scheduling is divided into bursttransfer units. The DMA request generating means periodically issues theDMA request in the burst transfer units and performs DMA of the transferdata which cannot be scheduled during the period that the DMA of thetransfer data is not performed, thereby avoiding concentration ofspecific DMA and regularizing the DMA. Such a data transfer controlmethod can be realized so that a reduction in each buffer capacity andthe high efficiency of the data transfer become possible.

According to an image processing apparatus of claim 5 of the presentinvention, in the image processing apparatus of claim 3, the directmemory access settings holding means comprises: first controlinformation storage means for storing control information required fordata transfer control performed by the data transfer control means;second control information storage means for holding control informationrequired for the data transfer control concerning the direct memoryaccess to be preferentially executed; third control information storagemeans for, when the data transfer by the data transfer executing meansis interrupted, saving the control information required forretransferring the data later to store; and control information transfermeans for performing a transfer of the control information among thefirst through third control information storage means, and a transfer ofthe control information between the data transfer executing means, andthe second control information storage means and the third controlinformation storage means.

According to an image processing apparatus of claim 6 of the presentinvention, in the image processing apparatus of claim 3, the directmemory access adjusting unit comprises; data transfer request adjustingmeans for receiving a data transfer request from the encoding/decodingmeans or the direct memory access request generating means and selectinga classification of the data transfer to be executed next and a priorityof the data transfer; second data transfer classification holding meansfor holding a classification of the data transfer corresponding to thecontrol information held by the second control information storagemeans; second data transfer priority holding means for holding priorityinformation corresponding to the control information held by the secondcontrol information storage means; first data transfer classificationholding means for holding a classification of the data transfer which isbeing executed in the data transfer executing means; first data transferpriority holding means for holding priority information of the datatransfer which is being executed in the data transfer executing means;third data transfer classification holding means for holding aclassification of the data transfer corresponding to the controlinformation held by the third control information storage means; thirddata transfer priority holding means for holding priority information ofthe data transfer corresponding to the control information held by thethird control information storage means; and control information savemeans for executing data transfer control by using information of areservation end flag which shows completing an obtainment of the controlinformation by either of the data transfer request adjusting means, thefirst through third data transfer classification holding means, thefirst through third data transfer priority holding means, and the secondcontrol information holding means, and information of a save end flagwhich shows completing the storage of the control information held bythe third control information storage means in the first controlinformation storage means.

According to an image processing apparatus of claim 7 of the presentinvention, in the image processing apparatus of claim 6, the datatransfer request adjusting means selects a data transfer request whichhas the highest data transfer priority as well as is received earliestamong the ones from which classifications of the data transfer held bythe first through third data transfer classification holding means areexcluded of the received data transfer requests, as the data transfer tobe executed next.

According to an image processing apparatus of claim 8 of the presentinvention, in the image processing apparatus of claim 7, the datatransfer request adjusting means comprises: priority informationregistering means for registering priority information of the receiveddata transfer request; new data transfer request detecting means fordetecting classifications of the data transfer request newly registeredin the priority information registering means; data transfer requestorder registering means for registering classifications of the datatransfer request detected by the new data transfer request detectingmeans in order; and top priority proposed data transfer detecting meansfor detecting a classification of the data transfer request which hasthe highest data transfer priority as well as is received earliest amongthe ones from which classifications of the data transfer held by thefirst through third data transfer classification holding means areexcluded, from information registered by the priority informationregistering means and the data transfer request order registering means,and information held by the first through third data transferclassification holding means.

According to an image processing apparatus of claim 9 of the presentinvention, in the image processing apparatus of claim 8, the datatransfer request adjusting means changes priority information registeredby the priority information registering means in accordance with theresult detected by the top priority proposed data transfer detectingmeans.

As described above, according to the image processing apparatus ofclaims 5 through 9 of the present invention, there are provided the datatransfer executing means for executing the data transfer, and thecontrol means for receiving the data transfer request having priorityinformation to select the data transfer to be executed next and, in thecase where the priority of the selected data transfer is higher than thepriority of the data transfer which is being executed in the datatransfer executing means, interrupting the execution of the datatransfer executing means to start the next data transfer. Therefore,even when the data transfer is immediately required, if the datatransfer request having higher priority than the data transfer which isbeing presently executed is made, the data transfer which is beingpresently executed is temporarily interrupted, and high priority datatransfer can be executed without waiting for the completion of the datatransfer which is being presently executed. Therefore, the data transfercan be certainly completed within the required period.

In addition, as for the interrupted data transfer, the controlinformation required for the transfer resumption of this data is savedand stored. Therefore, as soon as the data transfer request with higherpriority than the interrupted data transfer is lost, the interrupteddata transfer can restart, thereby preventing the data transferefficiency as a whole from lowering.

Further, the data transfer priority can be freely set at the time of thedata transfer request by the data transfer request adjusting meansincluded in the control means. Therefore, efficient data transfercontrol becomes possible, and a great effect can be shown especially inthe case where the data transfer amount and processing priority arediverse, and many data transfer classifications coexist.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a structural block diagram of an image processing apparatusaccording to a first embodiment of the present invention.

FIG. 2 is a structural block diagram of a DMA request generating meanscomposing the image processing apparatus according to the firstembodiment of the present invention.

FIG. 3 is a diagram showing generation timings of the first DMA requestsignal generated in the DMA request generation means.

FIG. 4 is a diagram showing the adjustment relationship between the DMAwhich can be previously scheduled and the DMA of processor means.

FIG. 5 is a block diagram showing a structure of a data transfer controlapparatus in an image processing apparatus according to a secondembodiment of the present invention.

FIG. 6 is a block diagram showing a detailed structure of control meanscomposing the data transfer control apparatus according to the secondembodiment.

FIG. 7 is a block diagram of data transfer request adjusting meansshowing a detailed structure of the data transfer request adjustingmeans composing the control means as shown in FIG. 6.

FIG. 8 is a structural block diagram of a conventional image processingapparatus.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described withreference to FIGS. 1 through 8. The embodiments which are shown hereinare merely examples and the present invention is not limited to theseembodiments.

Embodiment 1

Hereinafter, an image processing apparatus A according to the presentinvention, which can apply a data transfer control method for realizingan efficient DMA, will be described as a first embodiment with referenceto the drawings.

FIG. 1 is a structural block diagram of the image processing apparatusA.

This image processing apparatus A comprises image input/outputprocessing means 100, input control means 101 for performing resolutionconversion of the input image and image noise removal processing usingthe input image and the previous frame image, an input image buffer 102which temporarily holds the output image data of the input control means101 before transferring the data from the input control means 101 to anexternal memory 111, a previous frame image buffer 103 which temporarilyholds the previous frame image data stored in the external memory 111before giving the same to the input control means 101, a sub-picturegeneration input buffer 104 which temporarily holds the display imagedata stored in the external memory 111 before giving the same tosub-picture generating means 105, sub-picture generating means 105 forperforming resolution conversion of the display image data stored in theexternal memory 111 into that of the sub-picture, a sub-picturegeneration output buffer 106 which temporarily holds sub-picture imagedata which generated by the sub-picture generating means 105, beforetransferring data from the sub-picture generation means 105 to theexternal memory 111, a sub-picture buffer 107 which temporarily holdsthe sub-picture image data stored in the external memory 111, beforegiving the same to display control means 110, a main picture buffer 108which temporarily holds the display image data which is stored in theexternal memory 111, before giving the same to the display control means110, a graphics buffer 109 which temporarily holds graphics data storedin the external memory 111, before giving the same to the displaycontrol means 110, an external memory 111 which stores data, withperforming region segmentation for different types of image data such asencoding target image, a sub-picture, a display image, and graphics, DMAcontrol means 112 for controlling the DMA between the image input/outputprocessing means 100 or the processor means 116 and the external memory111, DMA settings holding means 113 for holding respective settinginformation for performing the DMA control, address generating means 114for generating an address of the external memory 111 in accordance withthe DMA setting information, DRAM control means 115 for controllingwriting or reading of the external memory 111, the processor 116 whichcan be controlled by programs, encoding/decoding processing means 117for processing an image of the external memory 111 or code data byprogram control, and a DMA bus 118 which performs DMA between the inputimage buffer 102, the previous frame image buffer 103, the sub-picturegeneration input buffer 104, the sub-picture generation output buffer106, the sub-picture buffer 107, the main picture buffer 108, thegraphics buffer 109, the processor means 116, and the external memory111, DMA request generating means 119 for generating a DMA requesttiming of the image input and output processing means 100 and theexternal memory 111 on the basis of a video synchronizing signal, andDMA request adjustment means 120 for, when making the DMA request fromthe DMA request generating means 119 and the DMA request from theprocessor means 116, adjusting the DMA requests so as to preferentiallyexecute the DMA request from the DMA request generating means 119.

Further, structures of the image input/output processing means 100, theinput control means 101, the sub-picture generating means 105, thedisplay control means 110, the DRAM control means 115, the processormeans 116, the encoding/decoding means 117, and the DMA bus 118 amongmembers composing the image processing apparatus A are identical tothose of the respective component members having the corresponding samenames in the above-described image processing apparatus X, i.e., theimage input/output processing means 500, the input control means 501,the sub-picture generating means 505, the display control means 510, theDRAM control means 515, the processor means 516, the encoding/decodingmeans 517, and the DMA bus 518, respectively.

In addition, the input image buffer 102, the previous frame image buffer103, the sub-picture generation input buffer 104, the sub-picturegeneration output buffer 106, the sub-picture buffer 107, the mainpicture buffer 108, and the graphics buffer 109 among members composingthe image processing apparatus A are identical to the respectivecomponent members having the corresponding same names in theabove-described image processing apparatus X, i.e., the input imagebuffer 502, the previous frame image buffer 503, the sub-picturegeneration input buffer 504, the sub-picture generation output buffer506, the sub-picture buffer 507, the main picture buffer 508, and thegraphics buffer 509 in points of these functions, though the former isdifferent from the latter in points of the capacity.

FIG. 2 is a structural block diagram of the DMA request generation means119.

This DMA request generating means 119 is composed of frame detectingmeans 201 for detecting the frame head from a video verticalsynchronizing signal, line detecting means 202 for detecting the linehead from a video horizontal synchronizing signal, clock counting means203 for counting an operation clock after receiving a line head signalfrom the line detecting means 202 to reset a discrete value, linecounting means 204 for counting the line head signal from the linedetecting means 202 after receiving the frame head signal from the framedetecting means 201 to reset the discrete value, 1/2 line detectingmeans 205 for detecting the start time of the DMA in burst transferunits which can be previously subjected to the DMA scheduling, from thediscrete value of the clock counting means 203, line cycle countingmeans 206 for counting the line detecting signal from the 1/2 linedetecting means 205 after resetting the discrete value by the frame headsignal from the frame detecting means 201 and one cycle end signal,first request signal generating means 207 for generating the DMA requestsignal from the discrete values of the clock counting means 203, theline cycle counting means 206, and line counting means 204, efficientline period detecting means 208 for detecting an efficient line periodfrom the discrete value of the line counting means 203 and the detectingsignal of the 1/2 line detecting means 205, efficient line detectingmeans 209 for detecting an efficient line from the discrete value of theline cycle counting means 206, request signal detecting means 210 fordetecting the request timing of the DMA from the discrete value of theclock counting means 203, an AND circuit 211, second request signalgenerating means 212 which has the similar structure to that of thefirst request signal generating means 207 and generates the DMA requestsignal of the other data which can be previously subjected to the DMAscheduling, and Nth request signal generating means 213. Further, Ndenotes the number of data types which can be previously subjected tothe DMA scheduling.

Hereinafter, the image processing apparatus A so constructed will bedescribed.

Initially, an input image is always input with synchronized with a videosynchronizing signal at a constant rate. After the input image is inputto the input control means 101, the input control means 101 performsresolution conversion of the input image into the image size to beencoded. Thereafter, the input control means 101 temporarily stores thesame in the input image buffer.

As an example, tables 1 and 2 show line timings in the case ofperforming resolution conversion of an NTSC interlaced size in which anefficient input image size is 704 pixels×240 lines×2 fields into a CIFsize in which an intensity and a color difference are 352 pixels×288lines and 176 pixels×144 lines, respectively.

TABLE 1

TABLE 2

In tables 1 and 2, the “line number” is the line number of the inputimage. In the case of the NTSC image, the line number is either value of1 through 525, and the 22nd line through the 261st line and 285th linethrough 524th line are used as efficient lines. Further, the “efficientintensity data output” shows the output line timing of the efficientintensity data after performing resolution conversion, and the“efficient color difference data output” shows the output line timing ofthe efficient color difference data after performing resolutionconversion. Both of two pieces of color difference data Cb and Cr havethe identical line timings.

Next, tables 3 and 4 show the line timings when performing the DMA ofimage data which is subjected to resolution conversion by the inputcontrol means 101 through the input image buffer 102 to the externalmemory 111.

TABLE 3

TABLE 4

In tables 3 and 4, the “line number” is the line number of the inputimage. The “intensity data DMA” shows the line timing for performing theDMA of the intensity data to the external memory 111, and the “colordifference data DMA” shows the line timing for performing the DMA of thecolor difference data to the external memory 111.

In this image processing apparatus A, an actual DMA starts from the timewhen half of the one line time passes. For example, the first line ofthe intensity data of the CIF size is output from the input controlmeans 101 in the line number 25, and the DMA is performed between thelatter half of the line number 25 and the first half of the line number26. It is known from table 3 that the intensity data of the 5th and 6thlines among the intensity data of the CIF size performs the DMA of twolines of the CIF size during one line period from the latter half of theline number 29 to the first half of the line number 30.

Here, the input control means 101 performs noise removal processing ofthe input image by using the previous frame image. In this case, theprevious frame image stored in the external memory 111 is subjected tothe DMA to the previous frame image buffer 103, and noise removalprocessing is performed while reading the previous frame image from theprevious frame image buffer 103.

In addition, table 5 shows the line timings when performing the DMA ofthe previous frame image from the external memory 111 to the previousframe image buffer 103. Here, noise removal processing is performed onlywith respect to the intensity data, resulting in performing the DMA ofonly the intensity data.

TABLE 5

On the other hand, when the display image which is stored in theexternal memory 111 is displayed as the sub-picture, the sub-picturegenerating means 105 performs resolution conversion of the display imagewhich is transferred from the external memory 111 through thesub-picture generation input buffer 104 into the sub-picture size totemporarily store in the sub-picture generation output buffer 106.Thereafter, the resolution-converted display image is transferred fromthe sub-picture generation output buffer 106 to the external 111.

Table 6 shows the line timings when performing the DMA of the displayimage data of the intensity 704 pixels×480 lines and the colordifference 352 pixels×480 lines from the external memory 111 to thesub-picture generation input buffer 104. In this table 6, the intensitydata and the color difference data has the identical line timings.

TABLE 6

In table 6, when the line number is the line number of the display imageand in the NTSC image, it is either value of 1 through 525, and 22ndline through 261st line and 285th line through 524th line are used asefficient display lines.

Further, table 7 shows the line timings when performing the DMA of thegeneration sub-picture data of the intensity 352 pixels×240 lines andthe color difference 176 pixels×240 lines from the sub-picturegeneration output buffer 106 to the external memory 111.

TABLE 7

On the other hand, the display control means 110 reads the sub-picture,the main picture, and the graphics data from the sub-picture buffer 107,the main picture buffer 108, and the graphics buffer 109, respectively,and, after display composition, synchronizes the same with the videosynchronizing signal as the display image to output at a constant rate.

Table 8 shows the line timings in the case where the display position ofthe sub-picture is in the lower right hand corner of the display monitorand when performing the DMA of the sub-picture data of the intensity 352pixels×240 lines and the color difference 176 pixels×240 lines from theexternal memory 111 to the sub-picture buffer 107.

TABLE 8

Tables 9 and 10 show the line timings when performing the DMA of themain picture data of the intensity 352 pixels×576 lines and the colordifference 176 pixels×288 lines from the external memory 111 to the mainpicture buffer 108.

TABLE 9

TABLE 10

Further, table 11 shows the line timings when performing the DMA of thegraphics data of 352×480 lines from the external memory 111 to thegraphics buffer 109.

TABLE 11

As described above, the DMA line timings between the external memory 111and each buffer have been described. Next, the DMA scheduling during oneline period will be described.

Tables 12, 13, 14 and 15 show the DMA request timings during one lineperiod, and one line period is divided into 20 and is further dividedinto 4 to arrange the DMA which can be previously scheduled. The DMAsize which is executed by one DMA request is 88 bytes, and the DMAoperation frequency is 67.5 MHz. When the DMA bus width is 16 bits, oneDMA is 44 cycles.

TABLE 12 previous frame image input image buffer DMA buffer DMAintensity intensity sub-picture generation input 67.5 data data bufferDMA MHz at 1 at 2- color color at 1 at 2- color color division clockline line difference difference line line intensity differencedifference No. number DMA DMA Cb data Cr data DMA DMA data Cb data Crdata 10 0 2150 ∘ ∘ 1 2194 ∘ ∘ 2 2238 3 2282 11 0 2365 ∘ 1 2409 ∘ 2 2453∘ 3 2497 12 0 2580 1 2624 2 2668 ∘ ∘ 3 2712 13 0 2795 ∘ 1 2839 2 2883 ∘3 2927 14 0 3010 1 3054 2 3098 3 3142 15 0 3225 ∘ ∘ 1 3269 ∘ ∘ 2 3313 33357 16 0 3440 ∘ 1 3484 ∘ 2 3528 ∘ 3 3572 17 0 3655 1 3699 2 3743 ∘ ∘ 33787 18 0 3870 ∘ 1 3914 2 3958 ∘ 3 4002 19 0 4085 1 4129 2 4173 3 4217

TABLE 13 main picture buffer DMA sub-picture generation intensity 67.5output buffer DMA sub-picture buffer DMA data MHz color color colorcolor at 1 at 2- color color graphics division clock intensitydifference difference intensity difference difference line linedifference difference buffer No. number data Cb data Cr data data Cbdata Cr data DMA DMA Cb data Cr data DMA 10 0 2150 1 2194 2 2238 ∘ ∘ 32282 11 0 2365 1 2409 2 2453 3 2497 12 0 2580 ∘ 1 2624 ∘ 2 2668 ∘ 3 271213 0 2795 1 2839 ∘ 2 2883 3 2927 14 0 3010 ∘ 1 3054 ∘ 2 3098 ∘ 3 3142 150 3225 1 3269 2 3313 ∘ ∘ 3 3357 16 0 3440 1 3484 2 3528 3 3572 17 0 3655∘ 1 3699 ∘ 2 3743 ∘ 3 3787 18 0 3870 1 3914 ∘ 2 3958 3 4002 19 0 4085 ∘1 4129 ∘ 2 4173 ∘ 3 4217

TABLE 14 previous frame image input image buffer DMA buffer DMAintensity intensity sub-picture generation input 67.5 data data bufferDMA MHz at 1 at 2- color color at 1 at 2- color color division clockline line difference difference line line intensity differencedifference No. number DMA DMA Cb data Cr data DMA DMA data Cb data Crdata 0 0 0 ∘ ∘ 1 44 ∘ ∘ 2 88 3 132 1 0 215 ∘ 1 259 ∘ 2 303 ∘ 3 347 2 0430 1 474 2 518 ∘ ∘ 3 562 3 0 645 ∘ 1 689 2 733 ∘ 3 777 4 0 860 1 904 2948 3 992 5 0 1075 ∘ ∘ 1 1119 ∘ ∘ 2 1163 3 1207 6 0 1290 ∘ 1 1334 ∘ 21378 ∘ 3 1422 7 0 1505 1 1549 2 1593 ∘ ∘ 3 1637 8 0 1720 ∘ 1 1764 2 1808∘ 3 1852 9 0 1935 1 1979 2 2023 3 2067

TABLE 15 main picture buffer DMA sub-picture generation intensity 67.5output buffer DMA sub-picture buffer DMA data MHz color color colorcolor at 1 at 2- color color graphics division clock intensitydifference difference intensity difference difference line linedifference difference buffer No. number data Cb data Cr data data Cbdata Cr data DMA DMA Cb data Cr data DMA 0 0 0 1 44 2 88 ∘ ∘ 3 132 1 0215 1 259 2 303 3 347 2 0 430 ∘ 1 474 ∘ 2 518 ∘ 3 562 3 0 645 1 689 ∘ 2733 3 777 4 0 860 ∘ 1 904 ∘ 2 948 ∘ 3 992 5 0 1075 1 1119 2 1163 ∘ ∘ 31207 6 0 1290 1 1334 2 1378 3 1422 7 0 1505 ∘ 1 1549 ∘ 2 1593 ∘ 3 1637 80 1720 1 1764 ∘ 2 1808 3 1852 9 0 1935 ∘ 1 1979 ∘ 2 2023 ∘ 3 2067

In tables 12 through 15, the “division No.” denotes the number when oneline period is divided, the “67.5 MHz clock number” denotes the cyclenumber during one line period at 67.5 MHz clock, the “input image bufferDMA” denotes a type of the DMA from the input image buffer 102 to theexternal memory 111, the “1 line DMA” denotes the request timing whenperforming the DMA of one line of the CIF size during one line period,the “2-line DMA” denotes the request timing when performing the DMA oftwo lines of the CIF size during one line period, the “previous frameimage buffer DMA” denotes the DMA from the external memory 111 to theprevious frame image buffer 103, the “sub-picture generation inputbuffer DMA” denotes a type of the DMA from the external memory 111 tothe sub-picture generation input buffer 104, the “sub-picture generationoutput buffer DMA” denotes a type of the DMA from the external memory111 to the sub-picture generation output buffer 106, the “sub-picturebuffer DMA” denotes a type of the DMA from the external memory 111 tothe sub-picture buffer 107, the “main picture buffer DMA” denotes a typeof the DMA from the external memory 111 to the main picture buffer 108,and the “graphics buffer DMA” denotes a type of the DMA from theexternal memory 111 to the graphics buffer 109.

The DMA request generating means 119 generates the DMA request signal atthe timings shown by ◯ in Tables 12 through 15.

FIG. 3 shows generation timings of a first DMA request signal which isgenerated in the DMA request generating means 119, that is, the DMArequest timings of color difference Cb data in the input image bufferDMA.

In FIG. 3, the “frame detecting means signal output” denotes a signaloutput timing showing the frame head of the frame detecting means 201,the “line detecting means signal output” denotes a signal output timingshowing the line head of the line detecting means 202, the “linecounting means discrete value” denotes a discrete value of a counter forinitializing the discrete value by a signal output of the framedetecting means 201 and adding 1 to the discrete value by the signaloutput of the line detecting means 202, the “efficient line perioddetecting means signal output 1” denotes a signal 1 showing theefficient line period from the discrete value of the line counting means204 and the signal output of the 1/2 line detecting means, the“efficient output image Cb data from input control means” denotes a Cbdata timing of an image outputted from the input control means 101 tothe input image buffer 102, the “1/2 line detecting means signal output”denotes 1/2 line time detected from the discrete value of the clockcounting means 203, the “line cycle counting means discrete value”denotes the discrete value of the counter for initializing the discretevalue by the signal output of the frame detecting means 201 or a finalsignal of the discrete value 4 and adding 1 to the discrete value by thesignal output of the 1/2 line detecting means 205, the “efficient linedecoding means signal output 2” denotes a signal 2 showing efficiency orinefficiency during one line period from the discrete value of the linecycle counting means 206, the “clock discrete value decoding signaloutput 3” denotes the request timing signal during one line period ofthe input image Cb buffer DMA obtained from the discrete value of theclock counting means 203, the “input image Cb buffer DMA request signal1” denotes a DMA request signal 1 which is generated by obtaining AND ofthe efficient line period detecting means signal output 1, the efficientline decoding means signal output 2 and the clock discrete valuedecoding means signal output 3, and the “input image Cb buffer DMA”denotes the DMA timing which is executed by the input image Cb bufferDMA request signal 1.

FIG. 4 shows an example of the adjustment relationship between the DMAwhich can be previously scheduled and the DMA of the processor means116.

When the DMA request adjusting means 120 receives the DMA request fromthe DMA request generating means 119, the DMA request adjusting means120 performs adjustment so as to execute the same with higher prioritythan the DMA request of the processor means 116, and executes the same.

To be more specific, initially, a transfer data group which can besubjected to scheduling of the DMA is divided into burst transfer units(DMA1˜DMA10), and the DMA is periodically performed for each of thedivided units. Next, while this transfer data is not subjected to theDMA (between the DAM 1 and the DMA 2), the DMA of the processor means116 as the transfer data which cannot be subjected to scheduling of theDMA is performed (DAM 11), and then this transfer data is transferred inaccordance with the DMA request of the processor means 116. As the DMAbus operating state, the DMA 11 results in coming next to the DMA 1.Further, while the DMA of the processor means 116 as the transfer datawhich cannot be subjected to scheduling of the DMA is being performed(DMA 13), the DMA request which can be scheduled is made (DMA 4), andthen the DMA 13 is once interrupted to preferentially perform the DMA 4.When the DMA 4 is completed, the DMA 13 is restarted to transfer therest. In this case, the DMA bus operating state becomes DMA 3-DMA 13-DMA4-DMA 13.

In this way, as shown in FIG. 4, when the DMA request is made from theprocessor 116 at the time when the DMA which can be previously scheduledis not executed, the DMA is immediately executed. If the DMA which canbe scheduled is executed, after completing the same, the DMA of theprocessor means is successively executed.

Then, if the DMA request which can be scheduled is made under theexecution of the DMA of the processor means which cannot be scheduled,the DMA of the processor means which is being executed is interrupted,and the DMA of the processor means is successively executed afterexecuting the DMA which can be scheduled.

As described above, according to this embodiment, the DMA which can besubjected to the DMA scheduling is periodically executed with priority,and during the period that the DMA which can be subjected to DMAscheduling is not executed, the DMA which cannot be subjected to the DMAscheduling is executed, thereby avoiding the concentration of specificDMA. More particularly, the request signal of the DMA which can besubjected to the DMA scheduling is generated after 1/2 line of the timethat the image input/output processing means outputs the request signal,or 1/2 line before the time required by the image input/outputprocessing means, thereby reducing the buffer capacity of the imageinput/output processing means.

Embodiment 2

The image processing apparatus comprising the data transfer controlapparatus in which, in the first embodiment described above, when thedata transfer request with high priority is made, the data transferwhich is being executed can be temporarily interrupted to start thetransfer of data with high priority will be described with reference tothe drawings.

FIG. 5 is a block diagram showing a structure of the data transfercontrol apparatus in the image processing apparatus A described in thefirst embodiment in advance. That is, the feature of the imageprocessing apparatus according to the second embodiment is the datatransfer control apparatus. Therefore, hereinafter, this part will bedescribed. Further, component parts of the image processing apparatusexcept the data transfer control apparatus and the operation thereof areidentical to those of the above-described image processing apparatus A.Therefore, the explanation thereof is omitted.

In FIG. 5, numeral 11 denotes control means for controlling each partcomposing the data transfer control apparatus, numeral 12 denotescontrol information storage means (first control information storagemeans) for storing control information required for data transfercontrol, numeral 13 denotes the data transfer executing means forexecuting the data transfer, numeral 14 denotes reservation controlinformation holding means (second control information storage means) fortemporarily holding control information required for data transfer whichis executed next, and numeral 15 denotes save control informationholding means (third control information storage means) for temporarilyholding control information from the data transfer executing means 13.In addition, numeral 16 denotes control information transfer means fortransferring control information from the control information storagemeans 12 to the reservation control information holding means 14, aswell as storing control information from the save control informationholding means 15 in the control information storage means 12. Numeral 17denotes a data transfer request source for requesting the data transfer,and numeral 18 denotes a storage apparatus of the data transfer target.

Further, the DMA settings holding means 113 is composed of the controlinformation storage means 12, the reservation control informationholding means 14, the save control information holding means 15, and thecontrol information transfer means 16. The control means 11 operates asthe DMA request adjusting means 120. The processor means 116 and the DMArequest generating unit 119 are included in the data transfer requestsource 17. In addition, the address generating means 114 and the DRAMcontrol means 115 are included in the data transfer executing means 13.

Hereinafter, the operation of the data transfer control apparatus soconstructed will be described.

The data transfer request source 17 requests the data transfer of thecontrol means 11 when the data transfer between the data transferrequest source 17 and the storage apparatus 18 is required. Here,priority information according to the emergency degree of the datatransfer is included in the data transfer request.

The control means 11 receives the data transfer request, and thenselects the data transfer to be executed next on the basis of thepriority information. The control means 11 controls the controlinformation transfer means 16 so as to obtain the control informationrequired for the data transfer from the control information storagemeans 12 and hold the same in the reservation control informationholding means 14.

The transfer of the control information to the reservation controlinformation holding means 14 is completed, and then, when it is judgedthat the data transfer to be executed next (requested) has higherpriority than the data transfer which is being executed in the datatransfer executing means 13, the control means 11 requests theinterruption of the data transfer which is being executed in the datatransfer executing means 13. In addition, when the data transfer of thedata transfer executing means 13 is interrupted, the control informationrequired when the data transfer is restarted next is saved to the savecontrol information holding means 15. Thereafter, the controlinformation which is held in the reservation control information holdingmeans 14 and is required for the next data transfer is transferred tothe data transfer executing means 13, whereby the data transferexecuting means 13 executes the next data transfer which is performedbetween the data transfer request source 17 and the storage apparatus 18on the basis of the control information.

The control means 11 controls the control information transfer means 16so as to store the control information required for again transferringthe data which is saved to the save control information holding means 15and the transfer of which is interrupted in the control informationstorage means 12.

The data transfer which is interrupted in order to execute the datatransfer with high priority controls the control information transfermeans 16 after completing the data transfer with high priority so thatthe reservation control information holding means 14 obtains the controlinformation which is necessary for the data transfer resumption from thecontrol information storage means 12 and transfers the same to the datatransfer executing means 13, thereby restarting the data transfer.

FIG. 6 is a block diagram showing a more detailed structure of thecontrol means 11 as shown in FIG. 5.

In FIG. 6, numeral 40 denotes data transfer request adjusting means forreceiving the data transfer request from the data transfer requestsource 17 and selecting the priority as compared with a classificationof the data transfer to be executed next. Numeral 41 denotes reservationdata transfer classification holding means (second data transferclassification holding means) for holding a classification of the datatransfer corresponding to the control information held by thereservation control information holding means 14. Numeral 42 denotesreservation data transfer priority holding means (second data transferpriority holding means) for holding priority information correspondingto the control information held by the reservation control informationholding means 14. Numeral 43 denotes execution data transferclassification holding means (first data transfer classification holdingmeans) for holding a classification of the data transfer which is beingexecuted in the data transfer executing means 13. Numeral 44 denotesexecution data transfer priority holding means (first data transferpriority holding means) for holding the priority information of the datatransfer which is being executed in the data transfer executing means13. Numeral 45 denotes save data transfer classification holding means(third data transfer classification holding means) for holding aclassification of the data transfer corresponding to the controlinformation held by the save control information holding means 15.Numeral 46 denotes save data transfer priority holding means (third datatransfer priority holding means) for holding the priority information ofthe data transfer corresponding to the control information held by thesave control information holding means 15. Numeral 47 denotes areservation end flag which shows completing the obtainment of thecontrol information by the reservation control information holding means14. Numeral 48 denotes a save end flag which shows completing thestorage of the control information held by the save control informationholding means 15 in the control information storage means 12. Numeral 49denotes interruption data transfer classification holding means forholding a classification of the data transfer interrupted in the datatransfer executing means 13. Numeral 50 denotes reservation save controlmeans for executing control by using information of the data transferrequest adjusting means 40, the reservation data transfer classificationholding means 41, the reservation data transfer priority holding means42, the execution data transfer classification holding means 43, theexecution data transfer priority holding means 44, the save datatransfer classification holding means 45, the save data transferpriority holding means 46, the reservation end flag 47, the save endflag 48, and the interruption data transfer classification holding means49.

FIG. 7 is a block diagram showing a more detailed structure of the datatransfer request adjusting means 40 as shown in FIG. 6.

In FIG. 7, numeral 31 denotes priority information registering means forregistering priority information of the received data transfer request.Numeral 32 denotes new data transfer request detecting means fordetecting a classification of the data transfer request which is newlyregistered in the priority information registering means 31. Numeral 33denotes data transfer request order registering means for registering aclassification of the data transfer request detected by the new datatransfer request detecting means 32 in order. Numeral 34 denotes toppriority proposed data transfer detecting means for detecting the datatransfer with top priority to be executed next from informationregistered in the priority information registering means 31 and the datatransfer request order registering means 33 and information held in thereservation data transfer classification holding means 41, the executiondata transfer classification holding means 43, the save data transferclassification holding means 45, and the interruption data transferclassification holding means 49.

Hereinafter, the operation of the data transfer request adjusting means40 so constructed will be described.

The priority information registering means 31 registers the priorityinformation corresponding to each of all data transfer classificationsin order to receive the requests of all data transfer classificationsfrom the data transfer request source 17. An example of FIG. 7 has seventypes of data transfer classifications, (a), (b), (c), (d), (e), (f),and (g). Here, it is assumed that the transfer priority has three typesof priorities, high priority, middle priority, and low priority. Here,when the data transfer request with low priority of the data transferclassification (c) is made from the data transfer request source 17,information showing low priority is registered in (c) of the priorityinformation registering means 31.

The data transfer request order registering means 33 registers all datatransfer classifications in order detected by the new data transferrequest detecting means 32. An example of FIG. 7 has registration parts(1)˜(7) corresponding to seven types of data transfer classifications.The data transfer classification registered in (1) is a classificationof the data transfer request which is received earliest. The larger thenumber in parentheses, such as (2), (3), becomes, the more newlyreceived data transfer classification is registered.

When the data transfer priority except the one corresponding to the datatransfer classification registered in the data transfer request orderregistering means 33 is registered, the new data transfer requestdetection means 32 detects the data transfer classification as the oneof the data transfer which is newly registered in the priorityinformation registering means 31.

The top priority proposed data transfer detecting means 34 selects thedata transfer request which is received earliest among the data transferrequests with highest priority of the received data transfer requests asthe data transfer which is executed with top priority.

However, when the same data transfer classification as the data transferclassification of the control information which exists in the datatransfer execution means 13, the reservation control information holdingmeans 14, and the save control information holding means 15 is selectedas the data transfer to be executed with top priority, a plurality ofcontrol information having the same data transfer classification insidethe data transfer control apparatus exists, thereby causing amalfunction. Therefore, the data transfer classification of the controlinformation which exists in the data transfer executing means 13, thereservation control information holding means 14, and the save controlinformation holding means 15 is required to be excluded from theproposed selection. Therefore, the data transfer classificationcorresponding to the control information held by the reservation controlinformation holding means 14 is held by the reservation data transferclassification holding means 41, the classification of the data transferwhich is being executed in the data transfer execution means 13 is heldby the execution data transfer classification holding means 43, and theclassification of the data transfer corresponding to the controlinformation held by the save control information holding means 15 isheld by the save data transfer classification holding means 45. Forexample, when low priority, low priority, middle priority, low priority,high priority, and middle priority are registered in (a), (b), (c), (e),(f), and (g) of the priority information registering means 31,respectively, the data transfer classification (e), the data transferclassification (b), the data transfer classification (g), the datatransfer classification (a), the data transfer classification (c), andthe data transfer classification (f) are registered in (1), (2), (3),(4), (5) and (6) of the data transfer request order registering means33, respectively, the data transfer classification (f) is held by theexecution data transfer classification holding means 43, and the datatransfer classification (g) is held by the save data transferclassification holding means 45, the top priority proposed data transferdetection means 34 outputs the data transfer classification (c) andmiddle priority which is the data transfer priority thereof as the datatransfer to be executed next with top priority. Further, (d) of thepriority information registering means 31 has no registration, and (7)of the data transfer request order registration means 33 also has noregistration.

In addition, when the data transfer with equal or lower priority ascompared with the priority of the interrupted data transfer wishes notto be executed prior to the resumption of the interrupted data transfer,it is possible by excluding the data transfer classification with lowerpriority than that of the data transfer classification of theinterruption data transfer classification holding means 49, in which thedata transfer classification interrupted in the data transfer executingmeans 13 is held, from the proposed selection.

For example, when the data transfer classification (g) is further heldin the interruption data transfer classification holding means 49 in theexample, there is no proposed data transfer to be executed next with toppriority. When all the control information of the save controlinformation holding means 15 is stored in the control informationstorage means 12, and the save data transfer classification holdingmeans 45 is reset, the top priority proposed data transfer detectingmeans 34 outputs the data transfer classification (g) and middlepriority which is the data transfer priority thereof as the datatransfer to be executed next with top priority, whereby the resumptionof the interrupted data transfer is executed prior to the other datatransfer with equal or lower priority.

Further, a change in the data transfer priority information which is setin the priority information registering means 31 becomes possible inaccordance with the request from the data transfer request source 17,thereby flexibly executing order control of the data transfer.

Next, the operation of the control means 11 will be described. Aclassification of the data transfer to be executed next and the prioritythereof are held by the reservation data transfer classification holdingmeans 41 and the data transfer priority holding means 42. Further, whenthe reservation end flag 47 is not set, the control information is notobtained by the reservation control information holding means 14 yet.Therefore, the reservation save control means 50 controls the controlinformation transfer means 16 so as to obtain the control informationcorresponding to a classification of the data transfer held by thereservation data transfer classification holding means 41 from thecontrol information storage means 12 and hold the same in thereservation control information holding means 14. Further, whencompleting the obtainment of all the control information, thereservation end flag 47 is set.

In addition, the classification and the priority of the data transfercorresponding to the control information stored in the controlinformation storage means 12 are held by the save data transferclassification holding means 45 and the save data transfer priorityholding means 46. Further, when the save end flag is not set, thecontrol information is not stored in the control information storagemeans 12. Therefore, the reservation save control means 50 controls thecontrol information transfer means 16 so as to store the controlinformation held by the save data transfer classification holding means15 in the region of the control information storage means 12corresponding to the classification of the data transfer held by thesave data transfer classification holding means 45. Further, when thestorage of all the control information is completed, the save end flag48 is set.

Further, when the data transfer request adjusting means 40 selects theclassification and the priority of the data transfer to be executednext, in the case where the priority of the selected data transfer ishigher than the priority held by the reservation data transfer priorityholding means 42, the reservation save control means 50 resets thereservation end flag 47 and further controls the reservation datatransfer classification holding means 41 and the reservation datatransfer priority holding means 42 so as to hold the classification andthe priority of the data transfer which is selected by the data transferrequest adjusting means 40 and preferentially execute the obtainment ofthe high priority data transfer.

Further, when the priority held by the reservation data transferpriority holding means 42 is higher than the priority held by theexecution data transfer priority holding means 44, and further thereservation end flag 47 is set, the reservation save control means 50requests the data transfer execution means 13 the interruption of thedata transfer.

Further, when the data transfer in the data transfer executing means 13is interrupted, or the data transfer is completed but there is controlinformation which is saved to the save control information holding means15, and further the save end flag 48 is set, the reservation savecontrol means 50 controls the save control information holding means 15so as to hold the control information, further controls the save datatransfer classification holding means 45 so as to hold the informationheld by the execution data transfer classification holding means 43, andcontrols the save data transfer priority holding means 46 so as to holdthe information held by the execution data transfer priority holdingmeans 44. Further, when the reservation end flag is set, the controlinformation required for the next data transfer execution is alreadyprepared in the reservation control information holding means 14.Therefore, the control information held by the reservation controlinformation holding means 14 is transferred to the data transferexecuting means 13, and the data transfer which is based on the controlinformation is started. Further, simultaneously, the information held bythe reservation data transfer classification holding means 41 is held bythe execution data transfer classification holding means 43, theinformation held by the reservation data transfer priority holding means42 is held by the execution data transfer priority holding means 44, thereservation end flag 47 is reset, and then the reservation data transferclassification holding means 41 and the reservation data transferpriority holding means 42 are reset.

Further, when the reservation end flag 47 is not set, the controlinformation required for the next data transfer execution is notprepared in the reservation control information holding means 14 yet.Therefore, the execution data transfer classification holding means 43and the execution data transfer priority holding means 44 are reset.

Further, when the data transfer in the data transfer execution means 13is completed, and the control information is saved to the save controlinformation holding means 15, the storage of the control information inthe control information storage means 12 is completed, and then theinformation registered by the priority information registering means 31and the data transfer request order registering means 33 whichcorrespond to the data transfer classification of the save data transferclassification holding means 45 is cancelled. In addition, when the datatransfer in the data transfer executing means 13 is completed, and thecontrol information is not saved to the save control information holdingmeans 15, the data transfer in the data transfer executing means 13 iscompleted, and then the information registered by the priorityinformation registering means 31 and the data transfer request orderregistering means 33 which correspond to the data transferclassification of the execution data transfer classification holdingmeans 43 is cancelled. Thereby, the control concerning the data transferclassification in the data transfer control apparatus is completed, andthe data transfer request source can newly request the data transfer ofthis data transfer classification.

In this way, according to this embodiment, there are provided thereservation control information holding means 14 for temporarily holdingthe control information required for the data transfer to be executednext, and the save control information holding means 15 for temporarilyholding the control information from the data transfer executing means13. When the priority of the data transfer request corresponding to thecontrol information held by the reservation control information holdingmeans 14 is higher than the priority of the data transfer which isexecuted by the data transfer executing means 13, the interruption ofthe data transfer which is executed by the data transfer executing means13 is requested. When the data transfer execution in the data transferexecuting means 13 is interrupted, the control information required forthe data transfer resumption is saved to the save control informationholding means 15, the control information held by the reservationcontrol information holding means 14 is transferred to the data transferexecuting means 13 so that the data transfer executing means 13 executesthe high priority data transfer. Therefore, when there is the transferrequest with higher priority than that of the data transfer which isbeing presently executed, the required data can be promptly provided.

Further, when the control information which is saved to the save controlinformation holding means 15 is stored in the control informationstorage means 12, and this control information is selected by the datatransfer request adjusting means 40 as the data transfer to be executednext, the control information required for the data transfer resumptionis obtained from the control information storage means 12 by thereservation control information holding means 14 to be output to thedata transfer executing means 13, and the transfer of the data, which isonce interrupted, is restarted.

INDUSTRIAL AVAILABILITY

As described above, the image processing apparatus according to thepresent invention relates to the data transfer control method in whichthe direct memory access (DMA) is performed by sharing one memory, andthe image processing apparatus which can apply this method, and is veryuseful as the one which realizes the efficient DMA by preventingspecific DMA from being concentratively generated, and simultaneouslysuppressing the increase in the circuit scale.

1. An image processing apparatus comprising: image input/outputprocessing means for inputting/outputting an image; a memory whichshares different types of image data by time division; encoding/decodingprocessing means for encoding or decoding data stored in the memory; anddata transfer control means for controlling a data transfer from thememory to the image input/output processing means or theencoding/decoding processing means, wherein a first transfer data group,which can be scheduled for direct memory access, is divided into bursttransfer units, the direct memory access of the burst transfer units isperiodically performed, and a second transfer data group, which cannotbe scheduled for direct memory access is subjected to the direct memoryaccess during at least a portion of the period that the first transferdata group is not subjected to the direct memory access; wherein anin-progress direct memory access of the second transfer data group issuspended during a scheduled direct memory access of the first transferdata group.
 2. The image processing apparatus of claim 1 wherein eachburst transfer unit is obtained by equally dividing the first transfergroup, and each burst transfer unit is periodically subjected to thedirect memory access.
 3. An image processing apparatus comprising: imageinput/output processing means for inputting/outputting an image; amemory which shares different types of image data by a time divisionmethod; and data transfer control means for controlling a data transferfrom the memory to the image input/output processing means orencoding/decoding processing means, wherein the data transfer controlmeans comprises: the encoding/decoding processing means encodes ordecodes data stored in the memory; direct memory access requestgenerating means for generating a transfer timing of data which can bepreviously subjected to the direct memory access scheduling; directmemory access request adjusting means for performing adjustment so as tointerrupt the direct memory access with the encoding/decoding processingmeans and preferentially execute the direct memory access of the imageinput/output processing means in the case where the direct memory accessrequest is made from the direct memory access request generating means;direct memory access settings holding means for holding settinginformation of the direct memory access; data transfer executing meansfor generating an address of the memory on the basis of direct memoryaccess setting information to transfer data by an instruction from thedirect memory access request adjusting means; and memory control meansfor controlling writing or read-out of the memory.
 4. The imageprocessing apparatus of claim 3 wherein the direct memory access requestgenerating means comprises: frame detecting means for detecting the headof the frame; first line detecting means for detecting the head of theline inside the frame; clock counting means for receiving a line headsignal from the first line detecting means to reset a discrete value,and thereafter counting an operation clock; line counting means forreceiving a frame head signal from the frame detecting means to reset adiscrete value, and thereafter counting a line head signal from thefirst line detecting means; second line detecting means for detecting astart time of the direct memory access in burst transfer units which canbe previously subjected to the direct memory access scheduling from thediscrete value of the clock counting means; line cycle counting meansfor resetting the discrete value by the frame head signal from the framedetection means and a signal after one cycle end and counting the linedetecting signal from the second line detecting means; efficientvertical period detecting means for detecting an efficient line periodfrom the discrete value of the line counting means and a detectingsignal of the second line detecting signal; efficient line detectingmeans for detecting an efficient line from the discrete value of theline cycle counting means; and request signal detecting means fordetecting a request timing of the direct memory access from the discretevalue of the clock counting means, and generates a direct memory accessrequest signal from a signal output of the efficient vertical perioddetecting means, a signal output of the efficient line detecting means,and a signal output of the request signal detecting means.
 5. The imageprocessing apparatus of claim 3 wherein the direct memory accesssettings holding means comprises: first control information storagemeans for storing control information required for data transfer controlperformed by the data transfer control means; second control informationstorage means for holding control information required for the datatransfer control concerning the direct memory access to bepreferentially executed; third control information storage means for,when the data transfer by the data transfer executing means isinterrupted, saving the control information required for retransferringthe data later to store; and control information transfer means forperforming a transfer of the control information among the first throughthird control information storage means, and a transfer of the controlinformation between the data transfer executing means, and the secondcontrol information storage means and the third control informationstorage means.
 6. The image processing apparatus of claim 3 wherein thedirect memory access adjusting unit comprises: data transfer requestadjusting means for receiving a data transfer request from theencoding/decoding means or the direct memory access request generatingmeans and selecting a classification of the data transfer to be executednext and a priority of the data transfer; second data transferclassification holding means for holding a classification of the datatransfer corresponding to the control information held by the secondcontrol information storage means; second data transfer priority holdingmeans for holding priority information corresponding to the controlinformation held by the second control information storage means; firstdata transfer classification holding means for holding a classificationof the data transfer under the execution in the data transfer executionmeans; first data transfer priority holding means for holding priorityinformation of the data transfer which is being executed in the datatransfer executing means; third data transfer classification holdingmeans for holding a classification of the data transfer corresponding tothe control information held by the third control information storagemeans; third data transfer priority holding means for holding priorityinformation of the data transfer corresponding to the controlinformation held by the third control information storage means; andcontrol information save means for executing data transfer control byusing information of a reservation end flag which shows completing anobtainment of the control information by either of the data transferrequest adjusting means, the first through third data transferclassification holding means, the first through third data transferpriority holding means, and the second control information holdingmeans, and information of a save end flag which shows completing thestorage of the control information held by the third control informationstorage means in the first control information storage means.
 7. Theimage processing apparatus of claim 6 wherein the data transfer requestadjusting means selects a data transfer request which has the highestdata transfer priority as well as is received earliest among the onesfrom which classifications of the data transfer held by the firstthrough third data transfer classification holding means are excluded ofthe received data transfer requests, as the data transfer to be executednext.
 8. The image processing apparatus of claim 7 wherein the datatransfer request adjusting means comprises: priority informationregistering means for registering priority information of the receiveddata transfer request; new data transfer request detecting means fordetecting classifications of the data transfer request newly registeredin the priority information registering means; data transfer requestorder registering means for registering classifications of the datatransfer request detected by the new data transfer request detectingmeans in order; and top priority proposed data transfer detecting meansfor detecting a classification of the data transfer request which hasthe highest data transfer priority as well as is received earliest amongthe ones from which classifications of the data transfer held by thefirst through third data transfer classification holding means areexcluded, from information registered by the priority informationregistering means and the data transfer request order registering means,and information held by the first through third data transferclassification holding means.
 9. The image processing apparatus of claim8 wherein the data transfer request adjusting means changes priorityinformation registered by the priority information registration means inaccordance with the result detected by the top priority proposed datatransfer detecting means.
 10. The image processing apparatus of claim 1,wherein a suspended direct memory access of the second transfer datagroup resumes after the scheduled direct memory access of the firsttransfer data group.
 11. An image processing apparatus, comprising: animage processor configured to input and output an image; a memory; anddata transfer controller configured to control data transfer from saidmemory to said image processor or an encoder/decoder, said data transfercontroller comprising: a direct memory access request generatorconfigured to schedule direct memory access; a direct memory accessinterrupter configured to interrupt direct memory access with saidencoder/decoder and to execute scheduled direct memory access of saidimage input processor if direct memory access is request by said directmemory access request generator; a store configured to hold settinginformation of direct memory access; a data transfer executor configuredto generate an address of said memory based on at least direct memoryaccess setting information to transfer data by an instruction from thedirect memory access request adjustor; and a memory controllerconfigured to control writing or read-out of the memory.